The role of the Flash controller: Hiding inherent imperfections
NAND Flash is an ideal non-volatile mass-storage solution, especially for mobile devices, because of its high speed, low power and physical robustness (it has no moving parts). It is replacing hard disk drives in many applications. The technology does have a number of inherent characteristics that need to be managed to ensure reliability, performance and lifetime, and it is the job of the Flash controller to do this. The controller provides the physical interface between the Flash memory devices and the host. It controls data reads and writes to make the most effective use of the Flash memory.
Characteristics of Flash memory technology
There are a number of features of Flash memory that the controller has to manage, hiding them from the host system. The first, and simplest, is mapping the logical block addresses provided by the host to physical locations within the Flash memory. The controller also has to keep this mapping updated as data is moved within the Flash memory.
Flash memory cells have a limited endurance of repeated program/erase cycles (because of the high voltages used for these operations). The controller will minimize the effects of this by using all blocks equally, with some form of “wear leveling” algorithm to choose the least-used block for writing new data. In order to detect errors when data is read from the Flash memory, the controller will use Error Correction Codes (ECCs) to create extra bits that are stored alongside the data. These are used when the data is read to detect and correct erroneous bits.
There are several reasons why these errors can occur, for example:
- The bit may have been randomly corrupted by natural background radiation
- The charge representing the bit value may have been disturbed by programming or reading nearby cells
- The data may have been written incorrectly because the cell has been weakened by repeated program/erase cycles
The first two of these are temporary: writing new data to the cell will correct the error. The last may be, or will soon become, a permanent error. The controller needs to mark the block containing the weakened cell as bad so it will not be used again. The controller will relocate the data in that block to a new one. When data is written to a page that already contains data then, because data can only be written to empty cells, the current page contents plus the new data will need to be copied to a new, erased page. The original page will then be marked as “invalid” and can be erased for re-use.
However, another characteristic of Flash memory is that data can only be erased at the level of blocks, which contain many pages. Because of the need to relocate pages when writing data, the Flash memory can end up with many partially used blocks and none free to be erased. Therefore, the controller needs to do “garbage collection”; consolidating the free pages into blocks, creating empty blocks that can be erased for re-use.
It is important that all of this data movement is done with minimal impact on the speed or latency of accesses by the host system. It must also ensure that neither the data nor the updated address mapping are lost if there is an unexpected power failure.
Matching the controller to the storage
The frequency of various types of errors varies, depending on the Flash memory. For example, read-disturb errors are more likely with multi-level cells (MLCs). Wear leveling and the timing of garbage collection will be affected by the amount of over-provisioning of spare cells in the Flash memory. The best type of ECC to use depends on the characteristics of the Flash array and the processing performance available in the controller. As a result, the controller needs to be carefully matched to the characteristics of the Flash memory array. Choosing the right Flash controller is vital to an efficient and reliable NAND Flash implementation.